1. Field of the Invention
The present invention relates to an embedded semiconductor memory, and in particular to a method and apparatus in which a Read Only Memory (ROM) is embedded in a Dynamic Random Access Memory (DRAM) by utilizing unused memory space of the DRAM.
2. Description of the Related Art
In a VLSI (Very Large Scale Integration) semiconductor chip design, both logic cells and memory cells may be incorporated onto a single chip. An embedded DRAM is a complex semiconductor circuit containing significant amounts of both DRAM and logic cells. This results in a compact design with minimal propagation distances between the logic cells and the memory cells. Embedded DRAM also offers the advantages of simpler system-level design, fewer packages with fewer pins, reduced part count, and lower power consumption.
The dense integration of logic on a single system has created immense problems for the test engineer. Often, the only way to handle such complexity is to divide the system into independently testable blocks, called macro testing. One such block is the DRAM.
Memory tests on random access memory (RAM) integrated circuits, such as DRAMs and SRAMs and the like are typically performed by the manufacturer during production and fabrication and also by a downstream manufacturer of a computer or processor controlled system as well as by an end-user during computer initialization to determine if the circuits are operating as intended. The testing is typically performed by a memory controller or processor (or a designated processor in a multi processor machine) which runs a testing program.
Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable. In order to reduce the number of address lines and time required to conduct a memory test, the memory test may be done in a so-called compressed mode in which banks of memory locations are tested in parallel, with the memory locations of one bank being tested against those of another, rather than one at a time.
A modern DRAM memory cell or memory bit (mbit) 10 is illustrated in FIG. 1. It is formed of a transistor 12 and capacitor 14. The cell 10 is capable of holding binary information in the form of a stored charge on the capacitor. The binary information is defined as either a logic `1` or a logic `0`, depending upon the charge stored on the capacitor 14. The common node 16 of capacitor 14 is biased to a voltage V. Various leakage paths cause the stored capacitor charge to slowly deplete. To return the stored charge and thereby maintain the stored data state, the cell must be refreshed. The gate of transistor 12 is connected to wordline 20. When wordline 20 is activated, the charge stored on capacitor 14 is dumped onto digitline 22, causing the voltage of digitline 22 to either increase or decrease according to the charge stored by capacitor 14.
FIG. 2 illustrates a memory array formed by tiling a selected quantity of cells 10 of FIG. 1 together such that cells along a given digitline do not share a common wordline and cells along a common wordline do not share a common digitline. To read the data stored in a cell 30 of the array, cell 30 is accessed by wordline driver 50 activating wordline 52. When the transistor of cell 30 is turned on, the charge stored by the capacitor of cell 30 is dumped onto digitline 54, labeled D0. Digitline 54 is input into a sense amplifier 60. The other input to sense amplifier 60 is digitline 56, labeled D0*. The charge on digitline 54 from cell 30 creates a differential voltage between digitlines 54 and 56. This differential signal is read by sense amplifier 60 and an output associated with the logic state of cell 50 is output from the array on line 62.
Although the structure of the DRAM is simple, it is difficult to test because it is sequential, each address is uniquely addressable, and the DRAM is susceptible to a variety of fault conditions, each requiring a unique test. One method of testing an embedded DRAM is the built-in self test (BIST). Conventional (hardware-based) self-tests generally use a dedicated controller (i.e., a dedicated state machine such as a programmable logic array) and a data pattern generator which together generate test patterns and then cycle the DRAM through a predefined sequence of operations. However, such self tests suffer from the disadvantage that a large amount of on-chip hardware may be required to create the data pattern generator.
A standard DRAM, called a "commodity" DRAM, has a very specific array core size defined by powers of 2 (for example a 64K block or a 256K block). When used in an embedded application, this may not be the case. For example, the application may require less than a standard commodity block of memory. The options would be to produce a special DRAM array core size with the specific block size required, or to provide a standard commodity block and not use all of the memory space available in that block. It is preferable to provide a commodity block DRAM, since there are several advantages in keeping the basic core block a constant size, i.e., defined with respect to a power of 2. These advantages include design throughput and controlled, well-known time constants. Thus, when a commodity DRAM is provided in an embedded application, there may be die space which is not utilized for any purpose.
FIG. 3 illustrates in block diagram form an application specific semiconductor chip 70 in which a DRAM is embedded. Semiconductor chip 70 comprises logic circuitry 72, which controls the specific application, and DRAM memory array 74. Data is passed between logic circuitry 72 and DRAM 74 over bus 76. Semiconductor chip 70 is connected to a processor system by I/O connector 78. An example of a specific application in which embedded DRAM is used is a circuit which combines a graphics accelerator and DRAM on the same chip. If the entire block of DRAM 74 is not used for the specific application of semiconductor chip 70, the memory not used will occupy space with no beneficial function. Thus, there may be unused memory space of an embedded DRAM which is not used efficiently.